Supporting Systolic and Memory Communication in iWarp

TM general computing; whereas systolic communication is iWarp is a parallel architecture developed jointly by efficient and well suited for speed critical applications. Carnegie Mellon University and Intel Corporation. The iWarp communication system supports two widely used interprocessor communication styles: memory A major achievement of the iWarp effort is the derivation of communication and systolic communication. This paper a common design to satisfy the requirements of both systolic describes the rationale, architecture, and implementation for and memory communication styles. This is made possible by the iWarp communication system. two important innovations in communication: (1) program access to communication and (2) logical channels. The former allows programs to access data as they are transmitted The sending or receiving processor of a message can perform and to redirect portions of messages to different destinations either memory or systolic communication. In memory efficiently. The latter increases the connectivity between the communication, the entire message is buffered in the local processors and guarantees communication bandwidth for memory of the processor before it is transmitted or after it is classes of messages. These innovations have provided a received. Therefore communication begins or terminates at focus for the iWarp architecture. The result is a the local memory. For conventional message passing communication system that provides a total bandwidth of 320 methods, both sending and receiving processors use memory MBytes/sec and that is integrated on a single VLSI communication. In systolic communication, individual data component with a 20 MFLOPS plus 20 MIPS long items are transferred as they are produced, or are used as they instruction word computation engine. are received, by the program running at the processor. Memory communication is flexible and well suited for iWarp is a trademark of Intel Corp. Warp is a servicemark of Carnegie Mellon University. This research was supported in part by the Defense Advanced Research Projects Agency, Information Science and Technology Office, under the title " Research on Parallel Computing", ARPA Order No. 7330, issued by DARPA/CMO under Contract MDA972-90-C-0035. Authors’ affiliations: R. Cohn, T. Gross, H. T. Kung, and J. Webb are with Carnegie Mellon University; S. Borkar, G. Cox, M. Levine, B. Moore, W. Moore, C. Peterson, J. Susman, J. Sutton, and J. Urbanski are with Intel; M. Lam, who was a Ph.D. student at Carnegie Mellon University, is now with Computer Systems Laboratory, Stanford University, Stanford, CA 94305. An earlier version of this paper appears in Proceedings of the 17th Annual International Symposium on Computer Architecture, Seattle, Washington, May 1990, pp. 70 81. operates at a frequency of 20 MHz, with the exception that the